Method and apparatus for removing encapsulating material from a packaged microelectronic device

ABSTRACT

A method and apparatus for encapsulating microelectronic devices. In one embodiment, the method includes removing a portion of encapsulating material that at least partially surrounds a microelectronic substrate by directing a source of laser radiation toward the encapsulating material. The method can further include exposing a surface of the microelectronic substrate, for example, to enhance a rate at which heat is transferred away from the microelectronic substrate. Alternatively, the encapsulating material can be removed to form heat transfer structures, such as pins or ribs, also to enhance a rate at which heat is transferred away from the microelectronic substrate. In still another embodiment, a portion of the encapsulating material or a support member to which the substrate is attached can be removed to define interlocking features that allow one microelectronic substrate package to be stacked on another and to resist relative movement between the two packages.

TECHNICAL FIELD

[0001] The present invention relates to microelectronic device packagesand methods and apparatuses for removing encapsulating material frommicroelectronic device packages.

BACKGROUND

[0002] Packaged microelectronic assemblies, such as memory chips andmicroprocessor chips, typically include a microelectronic die mounted toa substrate and encased in a plastic protective covering. The dieincludes functional features, such as memory cells, processor circuits,and interconnecting circuitry. The die also typically includes bond padselectrically coupled to the functional features. The bond pads arecoupled to pins or other types of terminals that extend outside of theprotective covering for connecting the microelectronic die to buses,circuits and/or other microelectronic assemblies.

[0003] In one conventional arrangement shown in FIG. 1A, a die 20 ismounted to a printed circuit board (PCB) 30 with an adhesive layer 23.The die 20 has internal functional features (not shown in FIG. 1A)coupled to die bond pads 33 a on an external surface of the die 20. Eachdie bond pad 33 a is connected with a wire bond 34 to a correspondingPCB bond pad 33 b on a surface of the PCB 30 facing away from the die20. Accordingly, the PCB 30 has a central aperture 31 that receives thewire bonds 34 and is aligned with the die bond pads 33 a. The PCB bondpads 33 b are connected to solder ball pads 32 with circuitry (notshown) internal to the PCB 30 for coupling the die 20 to other devicesor circuit elements.

[0004] To encapsulate the die 20, the die 20 and the PCB 30 arepositioned in a mold apparatus 40 by clamping a portion of the PCB 30between an upper mold portion 41 and a lower mold portion 42. The die 20is aligned with an upper cavity 43 in the upper mold portion 41 and thewire bonds 34 are aligned with a lower cavity 44 in the lower moldportion 42. A mold compound 60, such as an epoxy mold compound, isinjected into the mold cavities 43 and 44, and the encapsulated die 20and PCB 30 are then removed from the mold apparatus 40. The periphery ofthe PCB 30 is trimmed to form the device package 50 shown in FIG. 1B.Solder balls 35 are attached to the solder ball pads 32 for coupling thedevice package 50 to other devices, such as another PCB 30 a having bondpads 33 c aligned with the solder balls 35.

[0005] One drawback with the approach described above with reference toFIGS. 1A-1B for packaging the die 20 is that the mold apparatus 40 canallow the mold compound 60 to adhere to the solder ball pads 32 duringthe encapsulation process. For example, unclamped regions 45 of thelower mold portion 42 directly adjacent to the solder ball pads 32 arenot directly supported by any corresponding structure of the upper moldportion 41 when the mold portions 41 and 42 are clamped together (bycontrast, adjacent clamped regions 46 a of the lower mold portion 42 aresubjected to a direct normal force by corresponding clamped regions 46 bof the upper mold portion 41). Accordingly, the PCB 30 can flex awayfrom the unclamped region 45 and can allow the mold compound 60 to coverthe solder ball pads 32. The mold compound 60 on the solder ball pads 32can prevent the solder balls 35 from properly adhering to the solderball pads 32, and can accordingly interfere with a secure electricalconnection between the device package 50 and other devices or circuitelements to which the package 50 is attached. Furthermore, the flexingPCB 30 can place stresses on the die 20 that can potentially damage thedie 20.

[0006] One approach to addressing the foregoing drawback is to form atrench in the lower mold portion 42 adjacent to the solder ball pads 32for collecting any mold compound 60 that approaches the solder ball pads32. However, such trenches are not always effective and, as the dies 20become smaller, it can be difficult to find space between the lowercavity 44 and the solder ball pads 32 in which to position such atrench.

[0007] Another drawback with the conventional approach described abovewith reference to FIGS. 1A-1B is that it can be difficult to transferheat away from the die 20 through the mold compound 60. Accordingly, thedie 20 can overheat, which can limit the performance and/or the expectedlife of the die 20.

[0008] Still another drawback with the conventional arrangementdescribed above with reference to FIGS. 1A-1B is that it may not beconvenient to stack the device packages 50 on top of each other, atechnique that can increase the number of packages 50 provided per unitarea in compact electronic devices. In one conventional stackedarrangement, notches are cut into the edges of the PCB 30 of eachpackage 50 and a jig is used to align the notches of a first packagewith the notches of a second package stacked on the first package.However, this arrangement can be cumbersome and can cause damage to thedies 20, for example, if the jig is handled improperly.

SUMMARY

[0009] The present invention is directed toward methods and apparatusesfor encapsulating microelectronic devices. A method in accordance withone aspect of the invention includes disposing an encapsulating materialadjacent to a surface of the microelectronic substrate and exposing atleast a portion of the surface of the microelectronic substrate byremoving a portion of the encapsulating material adjacent to thesurface. The microelectronic substrate remains in an operable conditionafter the portion of the encapsulating material is removed. In a furtheraspect of the invention, the surface of the microelectronic substratecan be exposed by directing laser radiation toward the encapsulatingmaterial to ablate the material. In other aspects of the invention,portions of the encapsulating material can be removed to form heattransfer structures in the encapsulating material and/or to exposesolder ball pads of the microelectronic substrate.

[0010] The invention is also directed toward a microelectronic devicepackage. The package can include an operable microelectronic substratehaving a substrate surface and an encapsulating material at leastpartially covering the microelectronic substrate. The encapsulatingmaterial can have an external surface and an aperture extending throughthe external surface to the substrate surface, with a portion of thesubstrate surface exposed through the aperture. In other aspects of theinvention, the encapsulating material can have an interlocking featurepositioned to engage a corresponding interlocking feature of anotherdevice package to at least restrict relative movement between the devicepackages, for example, when the packages are stacked. In still anotheraspect of the invention, the device package can include heat transferstructures formed in the encapsulating material and projecting away fromthe substrate surface. The heat transfer structures can have at leastone exposed, external heat transfer surface and can include cylindricalrods, ribs, or other shapes.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1A is a partially schematic, cross-sectional side elevationalview of an apparatus for encapsulating a die in accordance with theprior art.

[0012]FIG. 1B is a partially schematic, cross-sectional side elevationalview of a packaged die formed with the apparatus shown in FIG. 1A.

[0013]FIG. 2 is a partially schematic, cross-sectional side elevationalview of an encapsulated microelectronic substrate having an exposedupper surface in accordance with an embodiment of the invention.

[0014]FIG. 3A is a partially schematic, cross-sectional side elevationalview of an apparatus for encapsulating a microelectronic substrate inaccordance with an embodiment of the invention.

[0015]FIG. 3B is a partially schematic, cross-sectional side elevationalview of an encapsulated microelectronic substrate having a portion ofencapsulating material removed in accordance with an embodiment of theinvention.

[0016]FIG. 4 is a partially schematic, cross-sectional side elevationalview of two microelectronic device packages positioned for stacking inaccordance with an embodiment of the invention.

[0017]FIG. 5 is a partially schematic, cross-sectional side elevationalview of two microelectronic device packages positioned for stacking inaccordance with another embodiment of the invention.

[0018]FIG. 6 is a partially schematic, top isometric view of a devicepackage having an encapsulating material with heat transfer structuresin accordance with yet another embodiment of the invention.

DETAILED DESCRIPTION

[0019] The present disclosure describes packaged microelectronic devicesand methods and apparatuses for packaging such devices. Many specificdetails of certain embodiments of the invention are set forth in thefollowing description and in FIGS. 2-6 to provide a thoroughunderstanding of these embodiments. One skilled in the art, however,will understand that the present invention may have additionalembodiments, or that the invention may be practiced without several ofthe details described below.

[0020]FIG. 2 is a partially schematic, cross-sectional side elevationalview of a device package 150 having a microelectronic substrate 120(such as a memory die or a processor die) with an exposed upper surface121. In one aspect of this embodiment, the microelectronic substrate 120has a lower surface 122 facing opposite the upper surface 121. The lowersurface 122 can include substrate bond pads 124 coupled to devicefeatures such as integrated circuits (not visible in FIG. 2) internal tothe microelectronic substrate 120. The microelectronic substrate 120 canbe mounted to a support member 130 (such as a PCB) by attaching anadhesive 123 between the lower surface 122 of the microelectronicsubstrate 120 and an upper surface of the support member 130. In afurther aspect of this embodiment, the support member 130 can havesupport member bond pads 133 connected to the substrate bond pads 124with wire bonds 134. Accordingly, the support member 130 can have anaperture 131 adjacent to the support member bond pads 133 through whichthe wire bonds 134 pass.

[0021] In one embodiment, the support member bond pads 133 are connectedto solder ball pads 132 with circuitry (not visible in FIG. 2) internalto the support member 130 to form a conductive link between the supportmember bond pads 133 and the solder ball pads 132. Solder balls 135 canthen be attached to the solder ball pads 132 for coupling the devicepackage 150 to other electronic components, as described above.Alternatively, the device package 150 can have other conductive elementsfor coupling to other electronic components.

[0022] In one aspect of an embodiment shown in FIG. 2, portions of themicroelectronic substrate 120 and the support member 130 are surroundedby an encapsulating material 160 to protect features of the devicepackage 150. For example, the encapsulating material 160 can include anepoxy mold compound that covers the substrate bond pads 124, the wirebonds 134, and the support member bond pads 133 after the wire bonds 134have been connected between the microelectronic substrate 120 and thesupport member 130. Accordingly, the encapsulating material 160 canprotect the electrical connection formed by the wire bonds 134 fromcorrosion and/or other environmental hazards.

[0023] In another aspect of an embodiment shown in FIG. 2, at least aportion of the encapsulating material 160 is removed from the devicepackage 150 in a region adjacent to the upper surface 121 of themicroelectronic substrate 120. Accordingly, the encapsulating material160 can have an opening 163 aligned with the upper surface 121. In oneaspect of this embodiment, the opening 163 extends through theencapsulating material 160 to the upper surface 121 to expose the uppersurface 121. Alternatively, a thin layer of the encapsulating material160 can remain adjacent to the upper surface 121 of the microelectronicsubstrate 120 by removing a layer of encapsulating material 160 having athickness less than the total thickness of the encapsulating material160 adjacent to the upper surface 121. For example, the thickness of theremoved layer can be greater than 0.003 inch in one embodiment, and canhave other values in other embodiments, depending on the total thicknessof the encapsulating material 160. In either embodiment, a sufficientamount of the encapsulating material 160 can be removed from the regionadjacent to the upper surface 121 to increase the rate at which heat canbe transferred away from the upper surface 121.

[0024] In one embodiment, the opening 163 in the encapsulating material160 is formed by positioning a laser source 170 proximate to the package150 and directing a laser beam 171 toward the upper surface 121 of themicroelectronic substrate 120. The laser beam 171 locally ablates theencapsulating material 160, forming a vapor 172 that can be convectedaway from the region adjacent to the device package 150. In one aspectof this embodiment, the opening 163 can be formed by repeatedly passingthe laser beam 171 over the device package 150, with each successivepass removing a portion of the encapsulating material 160 until theopening 163 has the desired dimensions. Alternatively, the entireopening 163 can be formed with a single pass of the laser beam 171. Ineither embodiment, a single opening 163 can extend over all or a portionof the upper surface 121 of the microelectronic substrate 120.Alternatively, the opening 163 can be one of a plurality of openings,each of which extends over a portion of the upper surface 121. Inanother embodiment, the aperture 163 can extend over the entire uppersurface of the package 150 so that the encapsulating material does notextend upwardly beyond the upper surface 121 of the microelectronicsubstrate 120.

[0025] In one embodiment, the power generated by the laser source 170can be from about 4 watts to about 25 watts, and the laser beam 171 canscan over the device package 150 at a rate of from about 125 mm/sec. toabout 2000 mm/sec. Adjacent scans can be about 0.025 inches wide and thelaser beam 171 can be pulsed at a frequency of from about 4 kHz to about25 kHz with a pulse width of about 8 microseconds. In other embodiments,the laser source 170 can generate laser beams 171 having othercharacteristics suitable for removing the encapsulating material 160.

[0026] In still further embodiments, other techniques can be used toremove a portion of the encapsulating material 160 to form the opening163. For example, radiation having wavelengths other than laserwavelengths can be directed toward the encapsulating material 160.Alternatively, chemical solvents, such as etchants, can be used toselectively remove portions of the encapsulating material 160 fromadjacent to the substrate upper surface 121 to form the opening 163. Inany of these embodiments, the techniques used to remove portions of theencapsulating material 160 are employed in a manner that does notadversely affect the operability of the microelectronic substrate 120.

[0027] One feature of an embodiment of the device package 150 describedabove with reference to FIG. 2 is that the upper surface of themicroelectronic substrate 120 is either exposed or has only a thin layerof encapsulating material 160 adjacent to it. An advantage of thisfeature is that heat can be more effectively and efficiently removedfrom the microelectronic substrate 120, for example, by convection orradiation from the substrate upper surface 121. Alternatively, a heatconductive heat sink can be attached to the exposed upper surface 121 tofurther increase the rate at which heat is transferred away from themicroelectronic substrate 120. In either of these embodiments, theincreased rate at which heat is transferred away from themicroelectronic substrate 120 can enhance the performance level and/orthe life expectancy of the microelectronic substrate.

[0028]FIG. 3A is a partially schematic, cross-sectional side elevationalview of a mold apparatus 140 for encapsulating the microelectronicsubstrate 120 in accordance with an embodiment of the invention. In oneaspect of this embodiment, the mold apparatus 140 can include an uppermold portion 141 configured to engage an upper surface 136 of thesupport member 130. Accordingly, the upper mold portion 141 can have anupper cavity 143 configured to receive the microelectronic substrate120. A lower mold portion 142 is positioned opposite the upper moldportion 141 to engage a lower surface 137 of the support member 130. Thelower mold portion 142 can include a lower cavity 144 configured toreceive the wire bonds 134, the support member bond pads 133 and thesolder ball pads 132. Accordingly, when the encapsulating material 160is introduced into the mold apparatus 140, it flows around themicroelectronic substrate 120 and the connections between themicroelectronic substrate 120 and the support member 130 to cover thewire bonds 134, the support member bond pads 133 and at least asubstantial portion of the solder ball pads 132.

[0029] In one aspect of this embodiment, the edges of the upper cavity143 are aligned with corresponding edges of the lower cavity 144.Accordingly, the edges of the upper cavity 143 define upper contactportions 146 a that are aligned with lower contact portions 146 bdefined by the edges of the lower cavity 144. As a result, the supportmember 130 is clamped uniformally from above and below. This is unlikesome conventional arrangements (such as the arrangement described abovewith reference to FIG. 1A) that have asymmetrically clamped PCBs thatcan allow portions of encapsulating material (flash) to penetratebetween the PCB and the contact portions of the mold.

[0030] Referring now to FIG. 3B, the device package 150 is removed fromthe mold apparatus 140 (FIG. 3A) after encapsulation and a portion ofthe encapsulating material 160 adjacent to the solder ball pads 132 isremoved to expose the solder ball pads 132 for attaching solder balls135 (FIG. 2). In one aspect of this embodiment, the laser source 170 candirect the laser beam 171 toward the encapsulating material 160 adjacentto the solder ball pads 132 to remove the encapsulating material 160from this region. Alternatively, etchants or other chemical agents orother non-chemical agents can remove selected portions of theencapsulating material 160, so long as the surfaces of the exposedsolder ball pads 132 are sufficiently clean to adhere to the solderballs 135.

[0031] In yet another alternative embodiment, an apparatus similar tothat described above with reference to FIG. 1A can be used toencapsulate the microelectronic substrate 120, even if the resultingpackage has flash extending over the solder ball pads 132. In thisalternative embodiment, the laser source 170 (or another agent forremoving the encapsulating material 160) can remove the flash from thesolder ball pads 132. An advantage of using the mold apparatus describedabove with reference to FIG. 1A is that existing mold apparatuses havingthis configuration can be used without alteration. Conversely, anadvantage of the apparatus 140 described above with reference to FIG. 3Ais that it can support the support member 130 equally from above andbelow, and can accordingly reduce the likelihood for inducing stressesin the microelectronic substrate 120.

[0032]FIG. 4 is a partially schematic, cross-sectional side elevationalview of two device packages positioned to form a stack 290 in accordancewith an embodiment of the invention. In one aspect of this embodiment,the stack 290 can include an upper package 250 a stacked on a lowerpackage 250 b (referred to collectively as device packages 250). Thedevice packages 250 are held in place relative to each other withcorresponding interlocking features 251 (shown as an upper portionfeature 251 a and a lower portion feature 251 b). For example, eachpackage 250 can include a support member 230 (such as a PCB), amicroelectronic substrate 220 attached to the support member 230, and avolume of encapsulating material 260 having an upper portion 260 a abovethe support member 230 and a lower portion 260 b below the supportmember 230. The upper portion 260 a can have an upper portion feature251 a that interlocks with a corresponding lower portion feature 251 bin the lower portion 260 b to resist relative motion between the twodevice packages 250.

[0033] In one embodiment, the upper portion feature 251 a can include atab or projection, and the lower portion feature 251 b can include arecess or cavity sized and shaped to removably receive the projection.In other embodiments, the features 251 can have other interlockingconfigurations. In still further embodiments, each device package 250can have more than one feature 251 to engage the adjacent devicepackage.

[0034] In any of the embodiments described above with reference to FIG.4, one characteristic of the interlocking features 251 is that they canbe molded directly into the encapsulating material 260. Accordingly, theposition of the features 251 can be consistent from one package 250 tothe next, providing greater assurance that the packages will be properlyaligned when stacked. Alternatively, the interlocking features can beformed by removing a portion of the encapsulating material 260, forexample, with a laser or a chemical process. In either embodiment,another characteristic of the interlocking features 251 is that they areintegrated in the packages 250. As a result, the packages 250 can bestacked without requiring additional jigs or tools, which can be timeconsuming to position and operate, and can cause damage to the packages250 if handled improperly.

[0035]FIG. 5 is a partially schematic, cross-sectional side elevationalview of two device packages 350 (shown as an upper package 350 a and alower package 350 b) positioned to form a stack 390 in accordance withanother embodiment of the invention. In one aspect of this embodiment,each device package 350 can include a support member 330, amicroelectronic substrate 320 on the support member 330, and anencapsulating material 360 surrounding the microelectronic substrate320. In a further aspect of this embodiment, the encapsulating material360 can be disposed on only an upper surface 336 of the support member330 and not a lower surface 337. Accordingly, the encapsulating material360 can include an upper interlocking feature 351 a and the supportmember 330 can include a corresponding lower interlocking feature 351 b(referred to collectively as interlocking features 351).

[0036] In one embodiment, the lower interlocking feature 351 b caninclude a cavity or recess in the lower surface 337 of the supportmember 330. In one aspect of this embodiment, the cavity can be sizedand shaped to accommodate a portion of the encapsulating material 360,without altering the encapsulating material 360 from a conventionalshape. Accordingly, the upper interlocking feature 351 b can be definedby a conventionally-shaped volume of encapsulating material 360.Alternatively, the lower interlocking feature 351 b can be sized andshaped to accommodate an upper interlocking feature 351 a that has aspecialized shape, for example, a protrusion generally similar to thatdescribed above with reference to FIG. 4. In still further embodiments,the interlocking features 351 can have other shapes and configurations,so long as the interlocking features 351 at least resist relative motionbetween the packages 350 and provide for alignment of the packages 350.

[0037]FIG. 6 is a partially schematic, top isometric view of a devicepackage 450 having heat transfer structures 480 in accordance withanother embodiment of the invention. In one aspect of this embodiment,the device package 450 includes a microelectronic substrate 420 at leastpartially enclosed with an encapsulating material 460. In one aspect ofthis embodiment, a portion of the encapsulating material 460 adjacent toan upper surface 421 of the microelectronic substrate 420 is removed toform a cavity 463 that exposes at least a portion of the upper surface421. Alternatively, a thin layer 466 of encapsulating material 460 canremain adjacent to the upper surface 421. In either embodiment, theencapsulating material 460 can also be formed into the heat transferstructures 480. For example, the heat transfer structures 480 caninclude pins 481 that project away from the upper surface 421 of themicroelectronic substrate 420, or project away from the thin layer 466of encapsulating material 460. The thin layer 466 can also transfer heataway from the microelectronic substrate 420, either alone or inconjunction with other heat transfer structures 480. The heat transferstructures 480 can include ribs 482 that project away from themicroelectronic substrate 420, or alternatively the heat transferstructures 480 can have other shapes and/or configurations for enhancingthe rate at which heat is transferred away from the microelectronicsubstrate 420. The heat transfer structures 480 can be formed with alaser process or a chemical or non-chemical process similar to thosedescribed above with reference to FIGS. 2-3. Alternatively, the heattransfer structures 480 can be formed according to other techniques, forexample, by molding the heat transfer structures directly into theencapsulating material 460.

[0038] One feature of an embodiment of the device package 450 describedabove with reference to FIG. 6 is that the heat transfer structures 480can be formed directly on the upper surface 421 of the microelectronicsubstrate 420. Alternatively, the heat transfer structures 480 can bepositioned on a thin layer 466 directly adjacent to the upper surface421. An advantage of either arrangement is that heat can be transferredmore directly from the microelectronic substrate 420 to the heattransfer structures 480 and from the heat transfer structures 480 to thesurrounding environment than in conventional arrangements that do notinclude the heat transfer structures 480.

[0039] Another feature of an embodiment of the device package 450described above with reference FIG. 6 is that the heat transferstructures 480 can be formed directly in the encapsulating material 460that surrounds the microelectronic substrate 420. An advantage of thisfeature is that a separate heat transfer structure (such as a heat sink)need not be separately attached to the microelectronic substrate 420.Accordingly, the thermal connection between the heat transfer structures480 and the microelectronic substrate 420 can be more secure andthermally transmissive than a connection formed by attaching aninitially separate heat sink.

[0040] From the foregoing, it will be appreciated that specificembodiments of the invention have been described herein for purposes ofillustration, but various modifications may be made without deviatingfrom the spirit and scope of the invention. For example, themicroelectronic substrates described above with reference to FIGS. 2-6can be supported by support members other than PCBs, including leadframes. The bond pads, solder ball pads, solder balls, and wire bondscan be replaced with electrically conductive terminals and connectorshaving other shapes and configurations. Furthermore, many of thefeatures described above with reference to FIGS. 2-6 can be combined inaccordance with further embodiments of the invention. For example, anembodiment of a microelectronic device package can include heat transferstructures in addition to interlocking features. Accordingly, theinvention is not limited except as by the appended claims.

1. A method for packaging a microelectronic substrate, comprising:disposing an encapsulating material adjacent to a surface of themicroelectronic substrate; and exposing at least a portion of thesurface of the microelectronic substrate by removing a portion of theencapsulating material adjacent to the surface of the microelectronicsubstrate with the microelectronic substrate in an operable conditionafter the portion of the encapsulating material is removed.
 2. Themethod of claim 1 wherein the microelectronic substrate has a firstsurface and a second surface facing opposite the first surface, thefirst surface having a plurality of bond sites for electricalconnections to the microelectronic substrate, and further whereinexposing a portion of a surface of the microelectronic substrateincludes exposing a portion of the second surface of the microelectronicsubstrate.
 3. The method of claim 1, further comprising: mounting themicroelectronic substrate to a support member with a first surface ofthe microelectronic substrate facing the support member and a secondsurface of the microelectronic substrate facing away from the supportmember; electrically coupling the microelectronic substrate to thesupport member; disposing the encapsulating material adjacent to boththe microelectronic substrate and the support member; and exposing atleast a portion of the second surface of the microelectronic substrateby directing laser radiation toward the portion of the encapsulatingmaterial adjacent to the second surface to ablate the portion of theencapsulating material.
 4. The method of claim 1, further comprising:selecting the microelectronic substrate to include a memory chip;mounting the microelectronic substrate to a printed circuit board; anddisposing the encapsulating material adjacent to both the printedcircuit board and the microelectronic substrate.
 5. The method of claim1, further comprising transferring heat directly away from the exposedportion of the surface of the microelectronic substrate.
 6. The methodof claim 1, further comprising convectively transferring heat directlyaway from the exposed portion of the surface of the microelectronicsubstrate.
 7. The method of claim 1 wherein removing a portion of theencapsulating material includes directing laser radiation toward theencapsulating material.
 8. The method of claim 1 wherein removing theportion of the encapsulating material includes directing a laser beamhaving a power of from about 4 watts to about 25 watts toward theencapsulating material.
 9. The method of claim 1 wherein removing theportion of the encapsulating material includes sequentially removinglayers of the portion of the encapsulating material by sequentiallyexposing the layers of encapsulating material to laser radiation.
 10. Amethod for packaging a microelectronic substrate, comprising: disposingan encapsulating material adjacent to the microelectronic substrate; andforming a heat transfer structure in an external surface of theencapsulating material by manipulating at least a portion of theencapsulating material to define at least one exposed heat transfersurface of the heat transfer structure.
 11. The method of claim 10wherein manipulating at least a portion of the encapsulating materialincludes removing a portion of encapsulating material by directing laserradiation toward the encapsulating material.
 12. The method of claim 10wherein the microelectronic substrate has a first surface and a secondsurface facing opposite the first surface, the first surface having aplurality of bond sites for electrical connections to themicroelectronic substrate, and further wherein manipulating at least aportion of the encapsulating material includes removing a portion of theencapsulating material adjacent to the second surface of themicroelectronic substrate.
 13. The method of claim 10, furthercomprising: mounting the microelectronic substrate to a support member;electrically coupling the microelectronic substrate to the supportmember; disposing the encapsulating material adjacent to both themicroelectronic substrate and the support member; and removing at leasta portion of the encapsulating material from a region proximate to themicroelectronic substrate.
 14. The method of claim 10 whereinmanipulating the encapsulating material includes removing a portion ofthe encapsulating material to expose a portion of a surface of themicroelectronic substrate initially covered by the encapsulatingmaterial.
 15. The method of claim 10 wherein forming a heat transferstructure includes forming a cylindrical rod of encapsulating materialprojecting away from the microelectronic substrate.
 16. The method ofclaim 10 wherein forming a heat transfer structure includes forming arib projecting away from the microelectronic substrate.
 17. A method forpackaging a microelectronic substrate, comprising: positioning at leastone of an encapsulating material and a support member adjacent to themicroelectronic substrate; and processing at least one of theencapsulating material and the support member to have an interlockingfeature by manipulating a portion of the encapsulating material and/orthe support member, the interlocking feature being configured to engagewith a corresponding interlocking feature of another microelectronicsubstrate package.
 18. The method of claim 17 wherein manipulating aportion of the encapsulating material and/or the support member includesdirecting laser radiation toward the encapsulating material and/or thesupport member to ablate the portion of the encapsulating materialand/or the support member.
 19. The method of claim 17 wherein theinterlocking feature is positioned in a first surface of theencapsulating material and wherein the method further comprises forminga second interlocking feature in a second surface of the encapsulatingmaterial facing opposite the first surface.
 20. The method of claim 17wherein processing the encapsulating material includes forming a recessin the encapsulating material.
 21. The method of claim 17 whereinprocessing the encapsulating material includes forming a projection inthe encapsulating material extending away from the microelectronicsubstrate.
 22. The method of claim 17 wherein the microelectronicsubstrate is electrically coupled to the support member and theinterconnecting feature is a first feature formed in the encapsulatingmaterial, and wherein the method further comprises processing thesupport member to form a second interconnecting feature configured toengage the first interconnecting feature of another microelectronicsubstrate.
 23. A method for positioning microelectronic device packages,comprising: aligning a first microelectronic device package having afirst microelectronic substrate and a first encapsulant with a secondmicroelectronic device package having a second microelectronic substrateand a second encapsulant; and engaging a first interlocking feature ofthe first microelectronic device package with a second interlockingfeature of the second microelectronic device package to at leastrestrict relative motion between the first and second microelectronicdevice packages.
 24. The method of claim 23, further comprising engaginga tab of the first encapsulant of the first microelectronic devicepackage with a recess in the second encapsulant of the secondmicroelectronic device package.
 25. The method of claim 23 wherein thefirst microelectronic device package includes a support member having acavity, and wherein the method further comprises receiving the secondencapsulant of the second microelectronic device package in the cavityof the support member of the first microelectronic device package.
 26. Amethod for packaging a microelectronic substrate, comprising:electrically coupling the microelectronic substrate to a support memberhaving a first surface and a second surface facing opposite the firstsurface, the first surface having a conductive bond pad; positioning thesupport member and the microelectronic substrate between two portions ofa mold with the first surface and the bond pad of the support memberfacing a first cavity in the first portion of the mold and themicroelectronic substrate facing a second cavity in the second portionof the mold; disposing an encapsulating material in the first and secondcavities of the mold to engage the microelectronic substrate and thebond pad; and removing a portion of the encapsulating material coveringthe bond pad to expose the bond pad while the microelectronic substrateremains in an operable condition.
 27. The method of claim 26, furthercomprising: aligning a first edge of the first cavity with a second edgeof the second cavity; and rigidly supporting the support member in themold by clamping the support member between the first and second edges.28. The method of claim 26 wherein removing the portion of theencapsulating material includes directing laser radiation toward theencapsulating material and ablating the portion of the encapsulatingmaterial.
 29. The method of claim 26 wherein removing the portion of theencapsulating material includes directing a laser beam having a power offrom about 4 watts to about 25 watts toward the encapsulating material.30. The method of claim 26 wherein removing the portion of theencapsulating material includes sequentially removing layers of theportion of the encapsulating material by sequentially exposing theencapsulating material to laser radiation.
 31. The method of claim 26,further comprising attaching a solder ball to the bond pad.
 32. A methodfor packaging a microelectronic substrate, comprising: mounting themicroelectronic substrate to a support member with a first surface ofthe microelectronic substrate facing the support member and a secondsurface of the microelectronic substrate facing opposite the firstsurface; electrically coupling the microelectronic substrate to thesupport member by passing wire bonds though an aperture in the supportmember and connecting one end of each wire bond to the support memberand an opposite end of each wire bond to the microelectronic substrate;encapsulating the microelectronic substrate and the support member bydisposing an encapsulating material over the support member and thesecond surface of the microelectronic substrate; and directing a sourceof laser radiation toward the second surface of the microelectronicsubstrate to remove at least a portion of the encapsulating materialadjacent to the second surface and expose the second surface.
 33. Themethod of claim 32, further comprising forming a heat transfer featurein the encapsulating material by removing a portion of the encapsulatingmaterial to define an exposed external surface of the heat transferfeature.
 34. The method of claim 32 wherein directing the source oflaser radiation includes directing a laser beam having a power of fromabout 4 watts to about 25 watts.
 35. The method of claim 32 whereindirecting the source of laser radiation includes engaging a laser beamwith the encapsulating material to remove a first portion of theencapsulating material and engaging the laser beam with theencapsulating material again to remove a second portion of theencapsulating material initially covered by the first portion of theencapsulating material.
 36. The method of claim 32 wherein removing aportion of the encapsulating material includes removing a layer ofencapsulating material having a thickness of greater than about 0.003inch.
 37. A microelectronic device package formed by a process,comprising: disposing an encapsulating material adjacent to themicroelectronic substrate; and exposing at least a portion of a surfaceof the microelectronic substrate by removing a portion of theencapsulating material adjacent to the surface of the microelectronicsubstrate with the microelectronic substrate in an operable conditionafter the portion of the encapsulating material is removed.
 38. Thedevice package of claim 37 wherein the microelectronic substrate has afirst surface and a second surface facing opposite the first surface,the first surface having a plurality of bond sites for electricalconnections to the microelectronic substrate, and further whereinexposing a portion of a surface of the microelectronic substrateincludes exposing a portion of the second surface of the microelectronicsubstrate.
 39. The device package of claim 37, further comprisingremoving a portion of the encapsulating material by directing laserradiation toward the portion of the encapasulating material to ablatethe portion of the encapsulating material.
 40. A microelectronic devicepackage, comprising: an operable microelectronic die having at least oneintegrated circuit and a die surface; and an encapsulating materialcovering at least a portion of the microelectronic die, theencapsulating material having an external surface and an apertureextending through the external surface to the die surface with a portionof the die surface exposed through the aperture.
 41. The package ofclaim 40, further comprising a support member adjacent to themicroelectronic die, and further wherein the microelectronic die iselectrically coupled to the support member.
 42. The package of claim 40wherein the microelectronic die has a first surface and a second surfacefacing opposite the first surface, the first surface having a pluralityof terminals for electrical connections to the microelectronic die, thesecond surface being exposed through the aperture in the encapsulatingmaterial.
 43. The package of claim 40 wherein the encapsulating materialincludes heat transfer structures extending transverse to the diesurface, the heat transfer structures having exposed, spaced-apartexternal heat transfer surfaces.
 44. The package of claim 40 wherein theencapsulating material includes an interlocking feature positioned toengage a corresponding interlocking feature of another device package toat least resist relative movement between the device packages.
 45. Amicroelectronic device package, comprising: an operable microelectronicsubstrate having a first surface and a second surface facing oppositethe first surface; and an encapsulating material and/or a support membercovering at least a portion of at least one of the first and secondsurfaces of the microelectronic substrate, the encapsulating materialand/or the support member having an interlocking feature positioned toengage a corresponding interlocking feature of another device packageand at least restrict relative movement between the device packages whenthe interlocking features of the packages are engaged with each other.46. The device package of claim 45 wherein the microelectronic substrateis at least partially encased in an encapsulating material and theinterlocking feature includes a projection in the encapsulating materialextending away from the second surface of the microelectronic substrateand positioned to be received in a corresponding recess of the otherdevice package.
 47. The device package of claim 45 wherein theinterlocking feature includes a recess in the encapsulating materialpositioned to receive a projection of the other device package.
 48. Thedevice package of claim 45, wherein the microelectronic substrate isattached to a support member and the interlocking feature includes arecess in the support member.
 49. A pair of microelectronic devicepackages, comprising: a first microelectronic device package having afirst microelectronic substrate and a first encapsulating material atleast partially covering the first microelectronic substrate, the firstencapsulating material having an external surface and an aperture in theexternal surface; and a second microelectronic device package having asecond microelectronic substrate and a second encapsulating material atleast partially covering the second microelectronic substrate, thesecond encapsulating material having an external surface and aprojection extending away from the external surface, the projectionbeing aligned with and received in the aperture of the firstencapsulating material when the first microelectronic substrate isadjacent to the second microelectronic substrate.
 50. The devicepackages of claim 49, further comprising a first support memberelectrically coupled to the first microelectronic substrate and a secondsupport member electrically coupled to the second microelectronicsubstrate.
 51. The device packages of claim 49 wherein at least one ofthe encapsulating materials includes a heat transfer structure extendingtransverse to the substrate surface, the heat transfer structures havingexposed, spaced-apart external heat transfer surfaces.
 52. Amicroelectronic device package, comprising: a support member having aconductive link with a first terminal and a second terminal, the secondterminal having a bonding surface to form electrical connections withthe second terminal; a microelectronic substrate engaged with thesupport member and electrically coupled to the first terminal of theconductive link; and an encapsulating material at least partiallycovering the microelectronic substrate and the support member, theencapsulating material extending over at least a substantial portion ofthe bonding surface of the second terminal of the conductive link. 53.The package of claim 52 wherein the support member includes a printedcircuit board, the first terminal of the conductive link includes a wirebond pad coupled with a wire bond to the microelectronic substrate, andthe second terminal includes a solder ball pad.
 54. The package of claim52 wherein the support member includes a printed circuit board having anaperture, and wherein the package further comprises a wire bondextending through the aperture from the microelectronic substrate to thefirst terminal.
 55. The package of claim 52 wherein the encapsulatingmaterial includes an epoxy.
 56. A microelectronic device package,comprising: a microelectronic substrate having a substrate surface; andan encapsulating material at least partially covering themicroelectronic substrate, the encapsulating material defining aplurality of heat transfer structures projecting away from the substratesurface, each heat transfer structure having at least one exposed,external heat transfer surface spaced apart from and facing a heattransfer surface of another of the heat transfer structures.
 57. Thepackage of claim 56 wherein the encapsulating material includes anepoxy.
 58. The package of claim 56 wherein the heat transfer structuresinclude at least one cylindrical rod of encapsulating materialprojecting away from the microelectronic substrate.
 59. The package ofclaim 56 wherein the heat transfer structures include at least one ribprojecting away from the microelectronic substrate.
 60. The package ofclaim 56 wherein the encapsulating material has an aperture and thesurface of the microelectronic substrate is exposed through the aperturein the encapsulating material.
 61. A microelectronic device package,comprising: a microelectronic substrate having a first surface and asecond surface facing opposite the first surface; a support memberhaving a first surface engaged with the first surface of themicroelectronic substrate and a second surface facing opposite the firstsurface, the support member having an aperture extending therethroughfrom the first surface to the second surface; a plurality of bondmembers extending through the aperture of the support member, the bondmembers being connected to the microelectronic substrate and the supportmember; and an encapsulating material disposed adjacent to themicroelectronic substrate and the support member, the encapsulatingmaterial having an opening through which a substantial portion of thesecond surface of the microelectronic substrate is exposed.
 62. Thepackage of claim 61 wherein the encapsulating material has at least oneheat transfer structure proximate to the second surface of themicroelectronic substrate, the heat transfer structure having an exposedexternal surface positioned to transfer heat from the microelectronicsubstrate.
 63. The package of claim 61 wherein the encapsulatingmaterial includes an interlocking feature positioned to engage acorresponding interlocking feature of another package to at least resistrelative movement between the packages.